140 Mbps system: two-way digitally encoded transmission link

OFC-140 Mbps system

To provide a two-way digitally encoded transmission link, operating at

139.264 Mbit/s, separate optical fibres used for each direction of transmission.

The system meets the requirements of a high quality trunk system to

international standards.

OPERATING PARAMETERS

Power Supply Requirements

Power Supply Voltages:

For 140 Mbit/s OLTU

+5V+/- 0.25 V, 0.5 A maximum

-5.2 V +/-0.15 V, 2.5 A maximum

For 140 Mbit/s OISU

+5V+/-0.25 V, 0.5 A maximum

-5.2 V +/-0.15 V, 1.8 A maximum

Power Consumption:

For 140 Mbit/s OLTU

16 W maximum

For 140 Mbit/s OISU

12 W maximum

On-board Fuses

For 140 Mbit/s OLTU

+5V: 3 A quick blow

-5.2 V: 7 A quick blow

For 140 Mbit/s OISU

+5V: 3 A quick blow

-5.2 V: 7 A quick blow

Interface conditions (for 140 Mbit/s OLTU only)

Traffic Input and Output Signals

139264 Kbit/s interface +/-15 ppm Coded Mark Inversion (CMI) encoded.

Nominal Input and Output Impedances

75 Ohm unbalanced.

Input and Output Return Loss

7 MHz to 210 MHz

Input Cable Loss

:greater than 15 dB

The signal may be attenuated by any length of Coaxial Cable, with a square

root of frequency characteristic and attenuation from 0 to 12 dB at 70 MHz.

Input Jitter Limits (Minimum peak-to-peak)

1.5 UI;

for 200 Hz to 500 Hz, thereafter decreasing by 20

dB/decade up to 10kHz

0.075 UI;

Output Return Loss

7 MHZ to 210 MHZ

Output Pulse Shape

for 10 kHz to 3.5 Mhz

: greater than 15 dB

Within the limits of ITU-T Recommendations G.703, G703/Figure 19 and

G703/Figure 20.

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Output Jitter Limits (Maximum peak-to peak)

OFC-140 Mbps system

With a jitter free 139264 Kbit/s +/- 15 ppm traffic in signal applied to input

of the 140 Mbit/s OLTU:

0.75 UI;

0.075 UI;

for 200 Hz to 10 kHz

for 10 kHz to 3.5 MHz (with a probability of 99.9% when

measured over a period of 10 seconds).

Performance Limits (140 Mbit/s QLTU and 140 Mbit/s OISU)

Error Performance: -

Error ratio per section is equal or better than 1 in 10^th

for Poisson distributed errors.

Auxiliary Channels: -

Auxiliary Channel 1

1024 Kbit/s channel used, when required, for Engineering Order Wire

(EDOW)/Data channels. It includes the following channels:

-One 64 Kbit/s channel which provides an omnibus conferencing circuit

between all stations.

-One 64 Kbit/s channel which provides end-to-end EOW communication.

-One Asynchronous Full Duplex V11/RS422 data channel, which operates

at rates between 1200 bit/s and 9600 bit/s. The channel is accessible at all

stations.

-One Asynchronous Duplex V28/RS232 data channel, which operates at

300 bit/s. The channel is accessible to all stations.

Auxiliary Channel 2

256 Kbit/s channel used for SMU-SMU communication (e.g. protection

switching)

Network Telemetry

256 Kbit/s channel operating at 9.6 or 19.2 kbaud. Used for supervisory

and network purposes.

INTRODUCTION

GENERAL

The Modular 140 Mbit/s Optical Line System provides long distances

transmission link operating at a nominal wavelength of 1300 mm. The

equipment has the capacity to handle at least 1920 telephone channels or

139.264 Mbit/s of digital traffic.

A tie line system consists of two 140 Mbit/s Optical Line Terminal Units

(OLTUs), one at each Line Terminal Equipment (LTE) at each end of the

route. The 140 Mbit/s OLTUs provide the line coding/decoding and the line

transmit/receive apparatus for the electro-optic path.

For long distance transmission systems, two 140 Mbit/s Optical

intermediate Station Units (OISUs) are used at Intermediate station

Equipment (ISE) to provide two-way regeneration of the traffic. The

number of ISEs fitted is dependent on the length and type of route.

CONSTRUCTION

The 140 Mbit/s OLTUs are housed in a 14 VU shelf (High Speed Shelf or

64*2 Shelf). The shelf can be fitted with suitable bracket assemblies for

mounting in a standard 19 rack.

The 140 Mbit/s OLTUs fit in the lower 8 VU section of the shelf. Up to 4

units can be accommodated on a single High Speed Shelf. In a 64*2 Shelf

only one 140 Mbit/s OLTU can be fitted.

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OFC-140 Mbps system

Each unit uses a multilayer glass fibre printed wiring board. Mounted on

the main unit on four pillars is the Receiver Module, which is contained in a

metal screening can. The electrical interface between the Receiver Module

and the main unit is via a 15-way D-type connector. Each unit is fitted with

a front panel, which contains a red Alarm LED, and a 6-way test socket.

The 140 Mbit/s OLTU also contains two coaxial monitor points. Each front

panel contains two knurled jackscrews, which are used to secure the unit

into the shelf.

Connection with the shelf back plane is via two edge connectors,

designated PLL and PLU. PLL is a 96-way connector equipped with 66 pins

in three rows of 22 pins.

PLU is a 96-way connector equipped with 42 pins in three rows of 14 pins,

four coaxial inserts for traffic signal and an early earth pin. The traffic

connections for the 140 Mbit/s OLTU are extended by the back plane to the

coaxial connectors in the upper 6 VU section of the shelf.

Optical connections are made via optical adaptors mounted near the top of

the unit. Access to the adaptor is via the upper 6 VU cabling section of the

shelf.

Optical connections are made via optical adaptors mounted near the top of the

unit. Access to the adaptor is via the upper 6 VU cabling section of the shelf.l

Nominal dimensions of the unit, excluding connectors are 222*195*50

mm. Front and side views of the units are given in figure.

Details of the shelf and the associated units are given in the appropriate

section of this manual.

SYSTEM DESCRIPTION

140 Mbit/s OLTU is given in figure. Block diagrams of the optical transmitter

and receiver are given in figure.r

Transmit Direction

The 140 Mbit/s CMI signals, Normal and Standby, from the shelf connectors

enter the unit via coaxial inserts in the upper backplane connector. The two

inputs are equalized and amplified in order to compensate for up to 120 m

station cabling. The equalized signals are applied to Signal Fail Detectors and

the Service Protection Network (SPN) Switch in the CMI Codec gate array. The

Fail Detectors raise an alarm signal if the associated input signal is not

present. The SPN Switch selects one of the signal input ports as the active

input. The switch is controlled by the Shelf Monitor Unit (via the BUS Interface

Device (BID)). The Shelf Monitor Unit can be controlled via the Hand Held

Terminal.

The selected input from the SPN Switch is applied to the CMI/Binary

Converter, which converts the CMI data into binary. A Clock Extraction circuit

extracts a 139.264 MHz clock from the data, which is used by the converter.

The converter also monitors the CMI data for CMI violations, sending a signal

to the BID if a violation is detected.

In the event of the failure of the selected CMI input, an Alarm Indication

Signal (AIS) is injected into the transmit data. On the latest units, AIS

injection is for performed by the CMI Codec gate array using timing derived

from the 34.816 MHz clock from the receive section of the CMI Codec gate

array. On issue 1 units, AIS injection is performed by the Line Codec gate

array using timing derived from the external 2 MHz clock. When an AIS is

injected, an alarm bit (Tx distant Alarm on latest issue units, Tx Forward

Alarm on issue 1 units) is set in the overhead data to indicate to the far end

that an AIS has been injected in the transmit data.

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OFC-140 Mbps system

The 139.264 Mbit/s binary data and 139.4 MHz clock from the CMI/Binary

converter are applied to a Serial/parallel Converter which converts the serial

data in to four parallel data streams, each at 34.816 Mbit/s. The converter

uses a 34.816 MHz clock derived from 139.264 MHz clock. The parallel data

streams and the 34.816 MHz are applied to the transmit section of the Line

Codec gate array.

The Line Codec gate array receives four parallel data streams, each at 34.816

Mbit/s, and a 34.816 MHz clock. The data is justified, allowing subsequent

insertion of the overheads bits, and scrambled. The scrambled data is applied

to a parallel parity summation circuit, which produces a parity checksum,

which is carried in the overhead bits and is used for the error detection at

subsequent locations. The parallel data streams are applied to the multiplexer,

which combines the main data with the system data containing framing and

auxiliary channels.

Timing for the Line Codec gate array is derived by a 147.456 MHz Voltage

Controlled Oscillator (VCO). The VCO is controlled by a phase comparator,

which locks the VCO to the incoming 34.816 MHz clock (divided-by-17) or to

an 2 MHz clock (derived from the 4 MHz clock from the End-of-Shelf Unit)

from the BID. Selection of the timing signals is controlled, via the BID, by the

Shelf Monitor Unit. The selected 2 MHz can also be selected as the clock to

which the end-of-Shelf Unit master clock is locked.

The four parallel data streams, each at 36.864 Mbit/s, and the 36.864 MHz

clock are applied to a Parallel/Serial Converter which converts the parallel data

into a 147.456 Mbit/s serial data stream.

The 147.456 Mbit/s data and the 147.456 MHz clock from the Parallel/Serial

Converter are applied to the Optical Transmitter. The transmitter converts the

incoming 147.456 Mbit/s electrical data signal into corresponding light pulses.

The incoming data is retimed and is then applied to a laser current switch,

which provides the modulation current for the laser. The mean optical output

power of laser is stabilized at 3 dBm by a feedback circuit which monitors are

output of the laser photodiode and adjust the laser bias current in order to

keep the optical output constant. The bias current can be monitored at test

socket SK2 on the front panel of the unit.

A thermistor mounted inside the laser package controls a Peltier

Cooler/Header and heat sink, which together limit the operating temperature

range of the laser to 250 c +/- 300 C. If the laser exceeds the given range, a

Laser High Temperature Out of Limits alarm is raised. If the temperature

exceeds 350 C, a Laser High Temperature alarm is raised.

The mean optical output is monitored and a Source Power Out of Limits alarm

is raised if the mean power exceeds given limits. The laser bias is also

monitored as a Source Bias Out-of-Limits alarm raised if the bias current

exceeds 150% of normal.

Receive Direction

The incoming 147.4456 Mbit/s optical signal is applied to the receiver module,

which is contained in a screened can.

The incoming 147.456 Mbit/s optical signal is detected and converted to a

corresponding electrical signal by a germanium avalanche photodiode (APD).

The signal from the APD is applied to a front-end pre amplifier and then to the

Data Amplifier, which includes feedback. The Data Amplifier provides the

signals for the APD Bias Control Circuit, the Phase Locked Loop (PLL) clock

extraction circuit and the Regenerator.

The APD bias control Circuit contains a peak-peak detector, which produces

voltage proportional to the peak-peak amplitude of the signal. The output from

the detector is used to provide Automatic gain control (AGC) by controlling the

APD bias voltage (which controls the avalanche gain of the APD). This

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OFC-140 Mbps system

arrangement ensures that the optimum amplitude eye waveform is always

present at the input of the decision circuit, irrespective of the amplitude of the

optical input signal, which will vary with different route lengths. The AGC

voltage can be monitored at the front panel test socket SK2. A label on the

front panel correlates the AGC voltage with the optical input level.

The PLL, comprising a VCO, a phase detector, a data rectifier and a loop filter,

provides a jitter reduced 147.456 MHz clock. The clock is used by the

Regenerator to produce the regenerated data. A lock detection circuit in the

PLL ensures that the VCO sweeps through its entire frequency range if the

loop is unlocked. The output from this circuit is also used to detect loss of

signal input, when the VCO will continually sweep through its entire frequency

range. The 147.456 Mbit/s data and 147.456 MHz clock form the receiver are

applied to a Serial/Parallel Converter which produces data streams each at

36.864 Mbit/s. The parallel data streams, together with a 36.864 MHz clock,

are applied to the Line Codec gate array.

The parallel data streams are examined for the presence of the Frame

Alignment Word (FAW), the recognition of which is used to synchronise the

locally generated timing waveforms to the frame structure of the received

data. If frame alignment is lost, a Loss of Alignment (LOA) alarm is raised.

Once alignment is achieved, the parallel data streams are demultiplexed in

order to remove the overhead bits, which are output as required. The

demultiplexed data streams are then desrambled and dejustified.

A parity check is performed on the received data by comparing the parity

information in the overhead bits with the parity of the received data. Any

discrepancies result in a parity error signal. Any parity errors detected are also

added to the cumulative error count carried in the overhead bits. Both the

parity error count and the cumulative error count are output from the codec,

either one can be selected via a link to be applied to the BID. The parity errors

are also counted and raise an alarm if the errors exceed an EBER of 1 in 10^3

The auxiliary 1data and associated clock are output on the highways selected

via the BID, by the Shelf Monitor Unit. The auxiliary 2 data is output to the

Shelf Monitor Unit via the BID.

If either a LOA, a EBER 1 in 10^3 or a Line Signal Fail (from receiver) or a RX

Forward Fail alarm is raised for

Greater than 250 ms, an AIS is injected into the receive data and a System

Fail alarm is output on the backplane.

An AIS is also injected if a RX Distant Alarm is present, however, no Rx AIS

inject alarm is applied to the BID.

When an AIS is injected, the timing is locked to the external 2MHz clock and a

signal is sent to the transmit section of the Line Codec which sets the reverse

alarm bit in the transmit data (which indicates to the next station that AIS has

been injected). The reverse alarm bit is not set if a Rx Distant alarm is present

(i.e. the far end is injecting an AIS in the transmit data due to loss of CMI

input).

The 34.816 MHz clock required by the Line Codec gate array is derived from a

276.538 MHz VCO, phase locked to either the receive data or the external 2

MHz clock (when an AIS is injected). A double-loop phase-locked loop is used

which has a narrow bandwidth for jitter reduction. Similarly in the loop is

provided by a 17.408 MHz Voltage Controlled Crystal Oscillator (VCXO). The

output of the 278.538 MHz VCO is divided down in the CMI Codec to produce

the required clocks.

The four 34.816 Mbit/s Parallel data streams from the Line Codec gate array

are applied to a Parallel/Serial Converter in the CMI Codec gate array. The

converter uses the 34.816 MHz and 139.264 MHz clocks derived from the

278.538 MHz VCO.

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OFC-140 Mbps system

The serial 139.264 Mbit/s data from the Parallel/Serial Converter is CMI

encoded and then applied to a CMI Buffer Amplifier, which provides two

buffered CMI Interface signals (1 V into 75 W). These signals are output via

coaxial inserts in the backplane connector. Each output is also available, via a

26 dB attenuator, at a coaxial monitor point on the card front edge.

Alarm Function

On-board alarm signals are applied to the BID, which provides the interface

between the unit and the Shelf Monitor Unit. The BID latches the alarm

signals, which are assembled into serial form for transmission to the Shelf

Monitor Unit. The BID is polled at regular intervals by the Shelf Monitor Unit

via the alarm bus.

The BID also provides a number of latched outputs, sent via the Shelf Monitor

Unit, which allow certain on-card parameters to be set (e.g. AIS inject, SPN

Control). These outputs also control the red Alarm LED on the front panel of

the unit.

Certain critical alarms (i.e. Rx AIS inject, Tx AIS Inject, Line Signal Fall and Rx

Aux.2) cause a Request Executive Action (REA) signal to be sent to the BID,

which causes the Shelf Monitor Unit to respond immediately. The signal is

reset by the Executive Action Acknowledge (EAA) signal from the BID.

CMI Errors and either the Cumulative Errors or Parity Errors from the Line

Codec gate array are applied to the BID. The errors are counted over a one

second period synchronized by a 1 second synchronization pulse (SECP) from

the Shelf Monitor Unit. The errors counts are output on request to the Shelf

Monitor Unit.